1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device where a plurality of input/output (I/O) bit configurations are manufactured on one chip and one of the I/O bit configurations is selected and fixed by a mode setting circuit determined at a wiring step or a similar manufacturing step.
2. Description of the Related Art
Recently, as the operation speed of microprocessors has increased, high speed access is also required for a main memory which is Generally constructed by a dynamic random access memory (DRAM) device, for example. In order to satisfy this requirement, synchronous semiconductor memory devices have been developed.
In a synchronous semiconductor memory device, when an external address as well as a data read/write command is supplied thereto, the external address is latched in a burst counter, so that a read/write operation is performed upon a memory section using this external address in the burst counter. Then, the content of the burst counter is incremented or decremented by receiving a synchronization clock signal, so that sequential read/write operations are performed upon the memory section using incremented or decremented addresses in the burst counter. Thus, in a synchronous semiconductor memory device, internal addresses are automatically generated inside of the device after an external address with a read/write command is received, and read/write operations are successively carried out by using the internal addresses, to thereby realize a high speed read/write operation based upon a burst operation.
On the other hand, two kinds of semiconductor memory devices such as a 4-bit I/O configuration memory device and an 8-bit I/O configuration memory device are manufactured on one chip, and one of the memory devices is selected and fixed at a final stage such as a wiring step or a bonding step. That is, when such two kinds of memory devices are manufactured, most circuitry layouts thereof are commonly designed, to reduce the design cost. Also, the mode setting or fixing of the two memory devices is carried out at a later stage of the manufacturing steps, to rapidly comply with customers' orders.
In a prior art synchronous semiconductor memory device in which two kinds of semiconductor devices such as an M-bit I/O configuration memory device and an M.times.2.sup.k -bit I/O configuration are manufactured on one chip, and one of the semiconductor devices is selected to be fixed at a later stage of the manufacturing steps, m-bit (m&gt;k) internal addresses are successively generated, and lower n bits (n=m-k) of the m-bit internal addresses are used to access a memory section both in an M-bit I/O configuration memory device mode and in an M.times.2.sup.k -bit I/O configuration memory device mode. Then, only in the M-bit I/O configuration memory device mode, the other k bits of the m-bit internal addresses are used to select one of 2.sup.k groups of data lines of the memory section and connect them to some of data input/output pins. Conversely, in the M.times.2.sup.k -bit I/O configuration memory device mode, all the data lines of the memory section are connected to all the data input/output pins regardless of the other k bits of the m-bit internal addresses. This will be explained later in detail.
In the above-described prior art synchronous DRAM device, however, since the same lower n bits of the m-bit internal addresses are used to access the memory section in the M-bit I/O configuration memory device mode and in the M.times.2.sup.k -bit I/O configuration memory device mode, the frequency of transition of the lower n bits of the m-bit internal addresses is so large as to increase the power consumption in decoders, amplifiers and the like of the memory section in the M-bit I/O configuration memory device mode. This also will be explained later in detail.